EP2AGX190FF35I3N

摘要:1–8Chapter1:OverviewfortheArriaIIDeviceFamilyArriaIIDeviceArchitecture■Diagnosticfeatures■SerialloopbackfromthetransmitterserializertothereceiverCDRfortransceiverphysicalcodingsublayer(PCS)andPMAdiagnostics■ParallelloopbackfromthetransmitterPCStothereceiverPCSwithbuilt-inselftest(BIST)patterngeneratorandverifier■Reverseserialloopbackpre-andpost-CDRtotransmitterbufferforphysicallinkdiagnostics■LoopbackmasterandslavecapabilityinPCIehardIPblocks■SupportforprotocolfeaturessuchasMSB-to-LSBtransmissioninaSONET/SDHconfigurationandspread-spectrumclockinginaPCIeconfigurationTable1–5listscommonprotocolsandtheArriaIIdedicatedcircuitryandfeaturesforimplementingtheseprotocols.Table1–5.Sampleo