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摘要:2.ArriaVGZDeviceDatasheetAV-51002|2019.04.262.2.3.1.1.High-SpeedClockSpecificationsTable117.High-SpeedClockSpecificationsforArriaVGZDevicesWhenJ=3to10,usetheserializer/deserializer(SERDES)block.WhenJ=1or2,bypasstheSERDESblock.ForLVDSapplications,youmustusethePLLsinintegerPLLmode.ArriaVGZdevicessupportthefollowingoutputstandardsusingtrueLVDSoutputbuffertypesonallI/Obanks.•TrueRSDSoutputstandardwithdataratesofupto230Mbps•Truemini-LVDSoutputstandardwithdataratesofupto340MbpsSymbolConditionsC3,I3LC4,I4UnitMinTypMaxMinTypMaxfHSCLK_in(inputclockfrequency)TrueDifferentialI/OStandards(183)ClockboostfactorW=1to40(184)5—6255—525MHzfHSCLK_in(inputclockfrequency)SingleEndedI/OStandardsClockb
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